1. Field of the Invention
The present invention relates to a phase change memory (PCM) device.
2. Description of the Related Art
As is known, phase change memory arrays are based upon memory elements which use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material forming the memory element, and precisely an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as calcogenides or calcogenic materials, can be used advantageously in phase change memory cells. The currently most promising calcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks.
In the calcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa. In the amorphous state, moreover, the resistivity depends to a marked extent upon the temperature, with variations of approximately one order of magnitude every 100° C. with a behavior typical of P-type semiconductors.
Phase change can be obtained by increasing the temperature locally. Below 150° C., both of the phases are stable. Above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the calcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then cool it off rapidly.
From the electrical standpoint, it is possible to reach the crystallization and melting temperatures by causing a current to flow through a crystalline resistive element that heats the calcogenic material by the Joule effect. FIG. 1 illustrates, in a simplified way, the behavior of the resistance of a calcogenic material as a function of the heating current and the logic values associated thereto, wherein RR indicates the resistance corresponding to the amorphous state (reset state or logic “0”) and RS indicates the resistance corresponding to the crystalline or polycrystalline state (set state or logic “1”).
The overall structure of a phase change memory is shown in FIG. 2. The memory array 1 of FIG. 2 comprises a plurality of memory cells 2, each including a memory element 3 of a phase change type and a selection element 4 formed here by an NMOS transistor. Alternatively, the selection element 4 may be formed by a bipolar junction transistor or a PN diode.
The memory cells 2 are arranged in rows and columns. In each memory cell 2, the memory element 3 has a first terminal connected to an own bitline 11 (with addresses BLn−1, BLn, BLn+1, . . . ), and a second terminal connected to a first conduction terminal of an own selection element 4. The selection element 4 has a control terminal connected to an own control line, also referred to as wordline 12 (with addresses WLn−1, WLn, WLn+1, . . . ), and a second conduction terminal connected to ground.
For selecting the memory element 3 belonging to a specific cell 2, for example the one connected to the bitline BLn and to the wordline WLn, the bitline 11 and the wordline 12 connected to the addressed cell (selected bitline BLn and selected wordline WLn) are brought to a high voltage so that the first terminal of the memory element 3 is biased at a first voltage V1 and the second terminal is biased at a second voltage V2 close to zero.
In conformance with the indicated resistance values, by reset operation the operation is meant that is performed for obtaining a reset cell (resistance RR) and by set operation the operation is meant that is performed for obtaining a set cell (resistance RS).
Writing a bit in a two-level cell is obtained by causing a current pulse of constant duration and amplitude to flow in the cell both for the set and the reset operation.
Because of the array configuration shown in FIG. 2, writing and reading a selected cell present criticalities. In fact, the cells 2 are in series to a bitline resistance RBL, designated by 15 in FIG. 3a. The bitline resistance RBL is a function of the topological position of the cell 2 along the bitline 11. In particular, the resistance RBL is zero for the cells 2 connected to the first wordline 12 (WL<0>) and is maximum for the cells 2 connected to the last wordline 12 (WL<N>).
Should a write operation be performed with a fixed biasing voltage (voltage VBL in FIG. 3a), the current flowing in the memory element 3 depends upon the topological position of the cell 2 to be written, i.e., upon the resistance RBL. In particular, if the cell 2 to be written is connected to the first wordline 12 (WL<0>), the voltage V1 applied to the first terminal is equal to VBL and thus determines a current I1 equal to:I1=(VBL−V2)/Rc where Rc is the resistance of the memory element 3. If, instead, the cell 2 to be written is connected to the last wordline 12 (WL<N>), the current 12 flowing in the cell is equal to:I2=(VBL−V2)/(Rc+RBL)which is less than I1.
The resistance value of each cell 2 after writing thus depends upon the position of the cell along the respective bitline 11, thus determining a spreading of the distribution of the resistances Rc of the cells 2.
If the selection element 4 is formed by a bipolar junction transistor instead of a MOS-type transistor, the dependence of the write current upon the topological position of the selected cell is even more marked, because the current flowing in the memory element 3 depends also upon the resistance of the wordline, as shown in FIG. 3b, where the wordline resistance is designated by 16 and is equal to RWL.
The above determines a further spreading of the distribution of the resistance values of the cells 2. On the other hand, having wide distributions of cell resistance leads to problems both during reading and during writing.
In fact, when a cell 2 is to be read that is in the reset state without damaging the information content thereof, it is necessary to apply across its memory element 3 a voltage V1-V2 that is not higher than a threshold voltage Vth, beyond which the memory element 3 can pass from the reset state (high reset resistance RR, see FIG. 1) to the set state (low set resistance RS). In practice, with current technologies and materials, threshold voltage Vth is about 1 V.
In the transition from the low field, low voltage range of operation up towards the threshold voltage Vth, the phase change device current increases faster than linear and becomes exponential in the region around Vth. The device current at Vth is defined as Ith. In order to be able to read a reset cell 2 by supplying a current in the cell without exceeding the threshold voltage Vth, it is necessary to supply a current less than Ith with sufficient operating margin. Ith for practical devices is in the range of 1-2% of the reset current. This translates to 5-10 μA and going lower for modern devices.
The generation of a precise read current of the order of magnitude of 1 μA begins to get complicated, in so far as for such values problems arise linked to process variations (mismatch, threshold voltage), temperature variations, etc.
Furthermore, with this current value, the resultant voltage across a reset cell having reset resistance RR=100 kΩ is equal to 100 mV. To distinguish therefore a set cell from a reset cell, there exists a margin of just 50 mV, intermediate between the above indicated voltage of 100 mV for reset resistance RR=100 kΩ and the resultant voltage for a set cell (close to 0 V). Providing additional margin, such as for example to limit to about 0.4-0.6 V the maximum voltage applied to the memory element during reading, greatly reduces these sense voltage differentials.